The present invention is generally directed to the utilization of redundant information sources which include a parity bit. More particularly, the present invention is directed to redundant computer memory systems which include a parity bit. Advantage is taken of the presence of the parity bit in a redundant environment to construct an extremely fault tolerant memory or information system. In particular, it is shown that simple majority voting logic circuits, when employed in this environment, provide an easily realized mechanism for error correction and error detection.
In the design of memory chips and memory systems, it is sometimes the case that not all memory array regions are required for a particular system application. In such circumstances, portions of the resulting memory array structure become available for other purposes. In particular, one of these other purposes is for providing redundant sources of information. Thus, when it is found in a particular memory array system that a portion of the array is not needed for the storage of required data, it is possible to devote other regions or array portions of the chip to the storage of redundant information. That is, the same information is stored in the multiple array portions. In those situations where one is able to store, an odd number of redundant pieces of information, it is possible to provide a simple voting circuit for each bit of information. In such voting circuits, the output bit is a zero or a one depending upon whether the majority of input binary signals is a zero or one. In fact, in computer systems where fault tolerance is critical, it is known to employ multiple processors or memory systems carrying out the same operations and wherein the result is determined by majority logic voting.
In such redundant systems, it is possible that simple single bit parity information may also exist within the individual redundant units. However, such parity information is usually treated simply as another bit in the redundant set of bits.
Accordingly, it is desirable to provide a mechanism which integrates the fault tolerant coverage provided by redundant copies with the fault protection provided by parity checking. In other words, it is desirable to be able to provide a cooperative relationship between simple redundancy and parity in a manner so as to provide the highest possible level of error detection and error correction.
It is noted that, while the description provided herein is primarily directed to a memory system, the principles and circuitry are equally applicable to fault tolerance when an arbitrary plurality of binary signal sources is employed. Thus in the present invention the signal sources are typically memory array structures containing redundant information; however, the present invention is in fact not so limited, but may extend to information sources other than semiconductor computer system memories.